The board, designed
like an engineer would.

Warts and all.

This is FaraEDA mid-design on our TC5 golden project. The header says 405 blocking · 17/44 verified · synthesis incomplete because that's the truth of this design at this moment. The Synthesis Coach on the right is explaining a duplicate-block card — and advising the engineer not to blanket-merge, because the three “transceivers” are different silicon that happen to share a name.

TC5 carousel · block diagram · FaraSYS baseline v1 pinned real screenshot

A design tool that always says yes is a liability. FaraEDA keeps a typed queue of everything unresolved — unconnected pins, open decisions, library gaps — and refuses to call the design done while any of it blocks. When it can't close the loop, it names exactly why.

Every circuit is designed in English first.

Before a single symbol is placed, each function gets a written design: what it does, which requirement asks for it, what parts it needs, how it connects. The circuit follows the words, and the words quote the requirement. That's what makes the trace real instead of decorative — and it's why a reviewer can read the design, not reverse-engineer it.

No lock-in. Bring your stack.

Clean export to the industry formats, netlist import from the tools you're leaving behind, and an open MCP interface so your own AI assistant can drive the canvas.

The hardware leg of the V.

FaraEDA builds against the baseline FaraSYS publishes and owes evidence back: design disclosures traced to requirements, change requests when the requirements need to move, and check results stamped with how they ran. Its sibling FaraSW does the same for the firmware that will run on this board — same project, same spine, traces meeting at the top.