FaraSYSearly access

The requirements
own the project.

Feed FaraSYS a specification. It builds the requirement set a program can actually stand on: audited for holes, quantified with typed parameters, allocated across disciplines, and published as versioned baselines the design tools consume. Everything downstream traces back here.

01
Import
Spec in; structure recognized
02
Audit
Holes flagged; questions raised
03
Quantify
Typed params, not prose numbers
04
Allocate
HW, PCB, SW — each to its tier
05
Baseline
Versioned, diffable, pinned
06
Publish
To FaraEDA, FaraSW & documents
The working surface

A requirement tree you can actually read.

Hierarchy on the left, requirements as rows, status you can see from across the room. If you've used a modern issue tracker, you already know how to drive it.

FaraSYSTC5 carousel baseline v3 HRS · SwRS published 37/44 verified 2 MIRs open
Project
Specs
Requirements
Allocation
Baselines
Change requests
Audit
Documents
TC5-SYS-REQ-005Tool presence shall be sensed on all 7 pocketsverified
TC5-HW-REQ-12Sensor input divider, 24 V domainHW24 V nomverified
TC5-HW-REQ-7MCU-side clamp ≤ 3.6 V under 24 V faultHW3.6 V maxverified
TC5-SW-REQ-1Poll all 7 channels at 100 Hz, debounce 3 samplesSW100 Hz minTest
TC5-SYS-REQ-011Carousel shall index within [TBD] secondsMIR-31 open
TC5-SYS-REQ-014RS-485 link to machine controller, 120 Ω terminationDesign_Constraint

Representative UI — the shipping product shares its shell with FaraEDA, shown in a real screenshot here.

The audit

It asks instead of guessing.

Every spec has holes. Most tools paper over them; most AIs invent something plausible to fill them. FaraSYS raises a Missing-Information Request: a specific question, tied to the requirements that need the answer, waiting for a human. The answer gets recorded with its provenance and flows to everything downstream.

  • Ambiguity, vagueness, and what-vs-how leakage flagged per requirement.
  • Customer constraints classified as constraints — not expelled as defects.
  • Unanswered questions block the gate. Silence is never treated as consent.
Missing information request · MIR-31
What is the maximum allowed index-to-index time? The spec gives a spindle dwell but no carousel figure. Used by TC5-SYS-REQ-011 and one derived timing requirement.
2.5 s worst case, confirmed with the customer 7/12 — G. (recorded, attributed, traceable)
Audit flag · implementation leakage
“…using an RC filter on each input” states a how, not a what. Proposed rewrite keeps the requirement; the RC choice moves down a tier. Accept / edit / keep as constraint.
Quantification

Numbers, not prose.

“About 24 volts” is not a requirement. Every quantity in a FaraSYS baseline is a typed parameter: value, unit, bound, tolerance, and — the part auditors love — where the number came from. Spec, human answer, or documented default. Open values are explicit TBDs the tools treat as data, so nothing downstream has to parse a sentence to find a voltage.

  • A design value copied from a requirement is checked against it mechanically. Any drift is an automatic finding.
  • Change a parameter and the blast radius downstream is computed, not guessed.
TC5-HW-REQ-12 · params
vin_nominal24 V · nominalsource: spec
clamp_max3.6 V · maxsource: spec
index_time_max2.5 s · maxsource: human answer · MIR-31
operating_temp_maxTBD · explicitopen · tracked
Baselines & change

Requirements change. That's the feature.

FaraSYS publishes numbered, immutable baselines, and every downstream tool pins the version it built against. When the design side hits something the requirements didn't anticipate — a discovered requirement, an infeasible ask, a plain question — it files a change request upstream. A human dispositions it. The decision ships in the next baseline, on the record.

  • Diffable change docs between baselines; full snapshots on demand.
  • Every CR disposition published back to the tool that filed it.
  • ReqIF export for the DOORS world you already live in.
Change requests · against baseline v3
◆ faraeda · derive_new
Discovered: on-board controller required to serve stepper + sensing + comms
disposition: accepted → TC5-SYS-REQ-016 in v4
◆ farasw · question
Debounce budget vs RTOS tick — is 3 samples at 100 Hz load-bearing?
disposition: answered · rationale attached
◆ faraeda · infeasible
IP67 + through-hole mandate conflict on connector family
disposition: modified → constraint relaxed in v4
Verification

“Verified” means a check ran.

Requirement quality is checked in rings: deterministic lint first (the INCOSE-style rules a machine can enforce), computed checks over the typed parameters second, and only then model judgment — per item, against named rules, never as a rubber stamp. The verified flag itself is written by a deterministic gate. No model touches it. No exceptions.

  • Evidence from FaraEDA and FaraSW lands on the requirement it verifies, stamped with the environment it ran in.
  • Cross-boundary conformance — design value vs requirement value — checked by code, not opinion.
singular · no escape clauseslint pass
divider output vs clamp_maxcomputed · pass
ERC evidence · faraeda · v3received
verification method missing · REQ-014flagged
Documents out

The paperwork writes itself. Because it's a render.

Requirement specs, trace matrices, and verification reports aren't documents someone maintains — they're views generated from the same data the tools work on. Standards-grade structure, docx and ReqIF out, always current because there's nothing to keep in sync.

System & discipline specs
Trace matrices
Verification reports
docx
ReqIF
StrictDoc-validated
In the family

The top of the V.

FaraSYS publishes the hardware baseline to FaraEDA and the software baseline to FaraSW through the same versioned contract. Design disclosures, change requests, and test evidence flow back up, and FaraSYS renders the whole picture: one trace from a system requirement to the board that carries it and the firmware that runs on it.